Embodiments of the inventive concepts relate to methods of fabricating integrated circuit devices and integrated circuit devices fabricated thereby.
Semiconductor devices may be required to have higher integration, higher density, lower power consumption, and faster operating speeds. A semiconductor device with highly integrated circuits may include a multi-layered interconnection structure, which may be formed of a metal material (e.g., aluminum). The formation of the aluminum interconnection lines may include depositing an aluminum layer on an insulating layer and etching it to expose the insulating layer.
However, the use of copper, instead of aluminum, as a material for the interconnection line, is growing as a design rule of the semiconductor devices decreases. This may be due to the relatively high electrical resistivity of aluminum. For example, as a width of an aluminum interconnection line decreases, its resistance increases, and thus it may be a difficult to realize semiconductor devices with higher operating speeds. Copper may offer advantages in cost and electrical conductivity, but there may be difficulty in patterning a copper layer using an etching technique. A damascene process may also be used to form copper interconnection lines. For example, the formation of the copper interconnection lines may include forming an insulating layer with a recess region for disposing a copper interconnection line, forming a barrier layer and a seed layer thereon, forming a copper layer to fill the recess region using an electroplating technique, and then removing the copper layer from a top surface of the interlayer dielectric.
However, a thickness of the seed layer may decrease with the decreasing design rule, which can lead to an increase in electrical resistance of the seed layer, especially for the crowded interconnection lines provided in a cell array region. As the result of the increase in electrical resistance of the seed layer, an electric current may not be sufficiently supplied to the cell array region during the electroplating process, such that the plating layer may be formed to have a void or cavity therein.
In addition, differences in pattern density between a peripheral circuit region and the cell array region may lead to an abrupt change in concentration of a plating solution, which may cause difficulties in uniformly forming the plating layer and in preventing the void from being formed.